Many large-scale integrated chips (ICs) such as microprocessors and advanced memory buffers (AMB) use a global clock as a timing reference to synchronize data and logic operations performed by different functional blocks on the chips.
As new generations of integrated chips (ICs) become faster and larger, it becomes more and more difficult to distribute the global clock signal to the functional blocks on an IC chip with minimum clock skew.
In addition, a clock distribution system for a high frequency global clock consumes more power as the frequency of the clock increases. When the frequency of the global clock increases, the wires for distributing the global clock across a large-scale IC chip dissipate more power, which can lead to performance degradation.
Furthermore, a traditional clock distribution network occupies lots of routing area, which may result in the need for a larger die size.
For example, FIG. 1 illustrates a prior art method of distributing clock signals using point to point connections. Such a clock distribution scheme uses employ point to point network topology, as shown in FIG. 1. For example, in FIG. 1, a clock source (11), such as a centralized Phase Lock Loop (PLL), generates a clock signal, which is provided to various functional blocks (e.g., 21, 23, . . . , 29) on an integrated circuit chip (13) as the global timing reference. Typically, the clock signal is distributed from the clock source (11) to each functional block (e.g., 21) through a differential wire pair, which provides the point to point connection from the clock source (11) to the corresponding function block (e.g., 21).
In FIG. 1, the use of a centralized clock source (e.g., PLL) can lead to reduced power consumption and less die size, when the clock distribution system is compared with a system that has distributed Phase Lock Loops (PLLs).
However, as the clock frequency increases, the distribution of a clock from a centralized source to function blocks on a large silicon die becomes increasingly difficult due to clock skew. Further, the clock distribution network may suffer from a large capacitive load which may cause high power consumption for clock distribution. Furthermore, as the number of functional blocks within an IC chip increases, the routing of the wires for the clock distribution network becomes more complicated; and the clock distribution network may occupy a larger die area due to the point to point connections.
FIG. 2 illustrates a prior art method of distributing clock signals using high impedance receivers in a daisy-chained clock distribution system. In FIG. 2, the global clock is distributed to a set of functional blocks (31, 33, . . . , 39) via a daisy chain that is terminated with a terminator (55). High impedance receivers (e.g., 41, 43, . . . , 49) are used on the daisy chain to receive the clock signal for the respective functional blocks (e.g., 31, 33, . . . , 39). The impedance receivers typically have impedance above 10 K ohms. An inductor (e.g., 53) is used between the transmission line (e.g., 51) and high impedance receiver (e.g., 41). Further details on such a clock distribution system can be found in “A 100 mW 9.6 Gb/s Transceiver in 90 nm CMOS for Next-Generation Memory Interfaces,” by Edoardo Prete, Dirk Scheideler and Anthony Sanders, in ISSCC 2006, SESSION 4, GIGABIT TRANSCEIVERS, 2006 IEEE International Solid-State Circuits Conference, pp. 88-89 and 640.
In the clock distribution system illustrated in FIG. 2, some power is wasted on the resistive termination load on the terminator (e.g., 55). Further, the clock distribution network may occupy a large die area due to the used of transmission lines (e.g., 51) and inductors (e.g., 53).